NMOS IC Fabrication Process

There are a large number and variety of basic fabrication steps used in the production of modem MOS ICs. The process could be designed for NMOS or PMOS or CMOS devices. The gate could use metal or poly-silicon (as described in this section for NMOS device). The substrate could be bulk silicon or silicon-on-sapphire (SOS). Finally, there are variations in the techniques to isolate the devices in the wafer to avoid parasitic transistors..

This post describes the silicon-gate process. The important distinguishing characteristics of such structure will be described later.

The fabrication sequence of n-channel MOS IC is shown in the figure below.

1.A thin layer of Si₃N₄ is deposited on entire wafer surface by chemical vapour deposition (CVD).The first photolithographic step defines area where transistors are to be fabricated. The Si₃N₄ is removed outside the transistor areas by chemical etching. The impurity, boron, is implanted in the exposed regions to suppress unwanted conduction between transistor sites. Next, SiO₂ layer of about 1 micro meters thickness is grown in these inactive, or field regions by exposing the wafer to oxygen in an electric furnace. This is known as selective or local oxidation process. The Si₃N₄ is impervious to oxygen and thus inhibits growth of the thick oxide in the transistor regions.

1. Next, the Si₃N₄ is removed by an etchant that does not attack SiO₂. A layer of oxide about 0.1 micro meters thick is grown in the transistor areas. Then a layer of poly-Si is grown over entire wafer by CVD process. The second photolithographic step defines the desired patterns for gate electrodes. Undesired poly-Si is removed by chemical or plasma etching. An n-type dopant, such as phosphorus or arsenic, is introduced into the regions that will become the source and drain of MOS device. For this, diffusion or ion implantation is used. The thick field oxide and the poly- silicon gate are barriers to the dopant, but in this process, the poly-Si becomes heavily n-type.
2. Again, an insulating layer, SiO₂, is deposited by CVD process. The third photolithographic step defines the areas in which contacts to the transistors are to be made, as shown in the figure given above. Chemical or plasma etching selectively exposes bare silicon or poly-Si in the contact areas.
3. For interconnection, Al is used. The fourth masking step patterns the Al as desired for circuit connections as indicated in the figure given above.

Above process is the simplest possible. For advanced processing of NMOS and CMOS, 7 to 12 masking steps are required.

Read more: http://www.circuitstoday.com/nmos-ic-fabrication-process#ixzz1Botynu1l
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