Formal estimation of CMOS inverter pair delay

The CMOS inverter pair has 7T time delay.The switching ON i.e; transition from logic 0 to logic 1 takes a delay of 2T and switching off i.e;transition from logic 1 to logic 0 takes a delay of 5T. The square Cg value doubles as the input is given to both NMOS and PMOS in a CMOS inverter.The Rs value too is different for pull up and pull down networks. The pull down with 10K ohms and pull up with 25K ohms is the normal assumption.The value of Rs can be made good by increasing the size of PMOS transistor. This, in turn, increases the square Cg value. The delay which is a product of Rs and square Cg , too increases.The speed of operation decreases. But there is a little gain in speed, as the wiring capacitances remain the same.